There are a variety of ways to organize and access data in integrated memories. Such memory access techniques include Random Access, Last In First Out (xe2x80x9cLIFOxe2x80x9d), and First In First Out (xe2x80x9cFIFOxe2x80x9d). In FIFO memories, the generally older data (first in) is released (first out) before the generally newer data is released. Such FIFO memories are generally used in data communications and digital processing systems.
FIFO integrated memories generally have a fixed width chosen in accordance with a given data width requirement. Accordingly, different applications having different data widths typically require different FIFO memories for matching the different data width requirements.
This disclosure presents an apparatus and method for selecting data in a FIFO memory array made up of a plurality of memory cells arranged in rows and columns, where each row of cells has an associated number of word lines selectively addressable by an associated row address, and each column of cells has an associated bit line that provides access to the memory cells of the associated column as enabled by the respective word lines; and the memory array includes an address decoder having an address input for receiving an input address for selecting word lines in accordance with the input address, and a programmable-width vertical pointer for providing read and write input addresses to the address input of the address decoder during associated read and write operations of the memory array, where the programmable-width vertical pointer modifies the read and write addresses during operations of the memory array and provides a FIFO memory functionality.